One of the major issues for DRAM products is defect reduction. Scrubber cleaning is the standard approach for removing the defects. However, due to product sensitivity, scrubber cleaning cannot always be implemented during certain stages of manufacture, particularly after the relatively fragile fin or cylinder capacitor is formed. Therefore, it is difficult to reduce product defects during the manufacture of fin or cylinder capacitor DRAMs.
To understand the defect problem during the manufacture of fin or cylinder capacitor DRAM manufacturing, it is important to understand how a typical fin or cylinder capacitor DRAM is manufactured.
FIGS. 1-7 schematically illustrate cross-sectional views of the structure formed at various stages in the fabrication of a fin capacitor using conventional processes. Referring to FIG. 1, a single crystal substrate 10 with a &lt;100&gt; crystallographic orientation is provided. In this embodiment adapted for DRAM fabrication, metal-oxide-semiconductor field effect transistors (MOSFETs), word lines and bit lines are formed in and on the substrate 10 in any suitable manner. In one embodiment, the word lines and bit lines are formed as follows.
A thick field oxide (FOX) region 12 is formed to provide isolation between devices on the substrate 10. Next, a silicon dioxide layer 14 is created on the top of surface of the substrate 10 to serve as the gate oxide for a subsequently formed MOSFET. A first polysilicon layer is then formed over the FOX region 12 and the silicon dioxide layer 14 using, for example, a low pressure chemical vapor deposition (LPCVD) process. The first polysilicon layer is doped in order to form a conductive gate 16A for the MOSFET structure.
A tungsten silicide layer is formed on the first polysilicon layer to improve interconnection between the gate polysilicon and subsequently formed metal interconnects. Next, a standard photolithography and etching process is performed to form gate structures 16A and word lines 16B. Active regions 20A, 20B are formed, using well-known processes to implant appropriate impurities in those regions and activate the impurities. Sidewall spacers 22 are subsequently formed on the sidewalls of the first polysilicon layer. Thereafter, active regions 24A, 24B (i.e., MOSFET's source and drain) are formed, using well-known processes to implant appropriate impurities in those regions and activate the impurities.
Then a first dielectric layer 26 is deposited on the gate structures 16A, word line 16B and the substrate 10 for isolation. A second dielectric layer 28 is subsequently formed on the first dielectric layer 26. The second dielectric layer 28 can be formed of any suitable material such as, for example, BPSG. Preferably, the second dielectric layer 28 is formed using a conventional chemical vapor deposition process. The second dielectric layer 28 is then planarized to improve the topography for the next processing step.
A silicon nitride layer 30 is formed on the second dielectric layer 28. Then, an oxide layer 32 is formed on the silicon nitride layer 30. A second polysilicon layer 34 is formed on the oxide layer 32. Finally, an oxide layer 36 is then formed on the second polysilicon layer 34. Thus, the sandwich structure of oxide/polysilicon/oxide is used to form a fin capacitor. In this embodiment, the oxide layers 32 and 36 can be formed of any suitable material such as TEOS and silicon dioxide. The oxide layers 32 and 36 and the second polysilicon layer 34 are formed using a conventional chemical vapor deposition process.
FIG. 2 shows the next stage of his method. The oxide layers 32 and 36, the second polysilicon layer 34, the silicon nitride layer 30, the first dielectric layer 26 and the second dielectric layer 28 are patterned and etched to form contact windows over the source/drain regions. Standard processes are used to form and pattern a photoresist layer 38 on the oxide layer 36 to define contact holes over selected source/drain regions 24. The photoresist layer leaves uncovered the contact holes, which are then etched through the oxide layers 32 and 36, the silicon nitride layer 30, the second polysilicon 34, the second dielectric layer 28, and the first dielectric layer 26 to expose a portion of the selected source/drain regions 24A. The resulting structure is shown in FIG. 3.
Turing to FIG. 4, a conformal third polysilicon layer 40 is then formed on the oxide 36 and in the contact hole. The third polysilicon layer 40 is formed using a conventional LPCVD process. Then, the oxide layer 36, the second polysilicon layer 34, and the third polysilicon layer 40 are patterned and etched. Standard processes are used to form and pattern a photoresist layer 42 on the third polysilicon layer 40 to define the pre-fin capacitor node over selected source/drain regions 24A. The oxide layer 36, the second polysilicon 34, and the third polysilicon layer 40 which are uncovered by photoresist layer 42 are etched down to the silicon oxide layer 32.
The structure shown in FIG. 4 is typical of the devices shown in the interior portions of the underlying wafer. However, the structure at the wafer's periphery edge is shown in FIG. 7. There are no contact holes and transistors in this structure. The second dielectric layer 28 is formed on the substrate 10. The silicon nitride layer 30 and the oxide layer 32 are formed on the second dielectric layer 28. The stacked structure, polysilicon layer 34/oxide layer 36/polysilicon layer 40, is formed on the oxide layer 32.
FIG. 5 shows the final stage of the manufacturing process. The oxide layers 36 and 32 are removed by wet etching to form a fin capacitor node. The wet etching process is typically performed by using HF or BOE solution. The wet etching process is controlled in time and typically, this etching step requires a relatively long period of time to remove the oxide layers 32 and 36. The resulting structure after wet etching is shown in FIG. 6.
However, on the wafer's periphery edge shown in FIG. 7, the oxide layers 36 and 32 are also removed by the wet etching process (indicated by the arrows 43). For several reasons known to those in the prior art, there are no contact holes in the stacked structure of polysilicon layer 34/oxide layer 36/polysilicon layer 40, and therefore, when the oxide layers 32 and 36 are removed, the polysilicon layers 34 and 40 will be "peeled" away from the underlying wafer and tend to float towards the interior of the wafer causing substantial product defects.
FIGS. 8-14 schematically illustrate cross-sectional views of the structure formed at various stages in fabricating a cylinder capacitor using conventional process. Referring to FIG. 8, a single crystal substrate 50 with a &lt;100&gt; crystallographic orientation is provided. In this embodiment adapted for DRAM fabrication, MOSFETs, word lines and bit lines are formed in and on the substrate 50 in any suitable manner, such as that described above.
After the MOSFET, word line, and bit line are formed, a second dielectric layer 58 is subsequently formed on a first dielectric layer 56. The second dielectric layer 58 can be formed of any suitable material such as, for example, BPSG. Preferably, the second dielectric layer 58 is formed using a conventional chemical vapor deposition process. The second dielectric layer 58 is then planarized to improve the topography for the next processing step. A silicon nitride layer 60 is formed on the second dielectric layer 58.
Then, the silicon nitride layer 60, the first dielectric layer 56 and the second dielectric layer 58 are patterned and etched to form contact windows over the source/drain regions. Standard processes are used to form and pattern a photoresist layer 61 on the silicon nitride layer 60 to define contact holes over selected source/drain regions 54A. The photoresist layer leaves uncovered the contact holes, which are then etched through the silicon nitride layer 60, the second dielectric layer 58, and the first dielectric layer 56 to expose a portion of the selected source/drain regions 54A. In this embodiment, a standard patterning and etching process is performed to form the contact hole to have the minimum width supported by the photolithography process. The planarization process performed on the second dielectric layer 58 facilitates the formation of the minimum width contact hole. The resulting structure is shown in FIG. 9.
FIG. 10 shows the next stage of the manufacturing process. A second polysilicon layer 64 is then formed on the silicon nitride layer 60 and in the contact hole. The second polysilicon layer 64 is formed using a conventional LPCVD process to completely fill the contact holes. The second polysilicon layer 64 is doped with phosphorus dopants with a concentration of about 10.sup.20 -10.sup.21 ions/cm.sup.2 to increase conductivity. Any suitable method may be used to doped the polysilicon such as, for example, in-situ doping. Then, an etching process is performed to remove the second polysilicon layer 64 over on the silicon nitride layer 60. The silicon nitride layer 60 serves as an etching end point.
An oxide layer 66 is formed on the silicon nitride layer 60 and the second polysilicon layer 64. The oxide layer 66 can be any suitable material such as TEOS and silicon oxide. The oxide layer 66 can be formed by conventional chemical vapor deposition process. Then, the oxide layer 66 is patterned and etched to form second contact window over the second polysilicon layer 64 and silicon nitride layer 60. The resulting structure is shown in FIG. 10.
Turning to FIG. 11, a conformal third polysilicon layer 70 is formed on the oxide layer 66 and in the second contact hole. The third polysilicon layer 70 is formed using a conventional LPCVD process. The third polysilicon layer 70 is doped with phosphorus dopants with a concentration of about 10.sup.20 -10.sup.21 ions/cm.sup.2 to increase conductivity. Any suitable method may be used to doped the polysilicon such as, for example, in-situ doping. An oxide layer 72 is formed on the third polysilicon layer 70. The oxide layer 72 can be any suitable material such as TEOS and silicon oxide. The oxide layer 72 is formed using a suitable chemical vapor deposition process to completely fill in the second contact holes and over the third polysilicon layer 70.
FIG. 12 shows the next stage of this method. The oxide layer 72 over the third polysilicon layer 70 is removed. An etching process(indicated by the arrows 73) is performed to remove the oxide layer 72 over the third polysilicon layer 70. This etching process can be a reactive ion etching process with a high selectivity ratio. The third polysilicon layer 70 serves as an etching end point. Then, the third polysilicon layer 70 over the oxide layer 66 is removed. An etching process (indicated by the arrows 73A) is performed to remove the third polysilicon layer 70 over the oxide layer 66. The etching process can be a reactive ion etching process with a high selectivity ratio. The oxide layer 66 serves as an etching end point. The resulting structure is shown in FIG. 12.
The structure shown in FIG. 12 is typical of the devices shown in the interior portions of the underlying wafer. However, on the wafer's periphery edge as shown in FIG. 14, for reasons known to those skilled in the art, there are no transistors in this structure and there is no contact between the polysilicon layers 64 and 70. The second dielectric layer 58 is formed on the substrate 50. The silicon nitride layer 60 is formed on the second dielectric layer 58. There is a contact hole through the silicon nitride layer 60 and the second dielectric layer 58 to expose the substrate 50. In the contact hole, similar to the interior wafer area, the polysilicon layer 64 fills in the hole. The oxide layer 66 is formed on the silicon nitride layer 60. Unlike the interior device wafer area, the second contact holes do not open through the oxide layer 66 to expose the polysilicon layer 64 and the portion of the silicon nitride layer 60. Therefore, an isolated pre-cylinder structure formed by the polysilicon layer 70 and the oxide layer 72 is formed in the center of the oxide layer.
Finally, the oxide layers 66 and 72 are removed to form a cylinder capacitor node. The preferred method of wet etching is performed by using HF or BOE solution. The resulting structure is shown in FIG. 13. At the same time, on the wafer's periphery edge shown in FIG. 14, the oxide layers 66 and 72 are also removed by the wet etching process. There is no contact between the polysilicon layers 70 and 64, and thus, when the oxide layers are removed, polysilicon layer 70 will "peel" away from the wafer substrate and result in floating particles that will cause defects in the wafer.
The present invention provides a simple improvement to the above described manufacturing process to prevent the generation of particles from the periphery edge of the wafer.